The present invention relates generally to signal receiving systems. In particular, the present invention provides phase coherence with frequency tracking of an input signal and for receiving weak signals in the presence of one or more stronger signals in communication systems. Other uses of the present invention includes digital systems applications, frequency synthesizer applications, and coherent demodulation and correlation applications.
Often, systems designed for receiving weak signals employ a Phase-Locked Loop (PLL) and, in some instances, two or more PLL's are used. In U.S. Pat. No. 4,500,851, two PLL's are connected essentially in cascade for regenerating a weak input signal. In this application, the loop parameters are chosen expressly to remove noise from an applied unmodulated sinusoidal signal having a fixed frequency.
U.S. Pat. No. 4,027,264 uses a PLL to provide a narrowband filter. In this application, a PLL is used for stripping voice signal information from an interfering tone to yield a signal-free duplicate of the interference for subtraction from a composite input signal. In this system, the output of VCO (40) is assumed to be shifted 90 degrees in phase from the input. This is approximately true only for very narrowband PLL circuits initially tuned to the frequency of the applied tone. For complete cancellation, an additional 90 degree phase shift is required, otherwise, only partial cancellation results. Therefore, an additional, external 90 degree phase shift circuit, insensitive to frequency, is required.
It is well known that obtaining phase shift circuits that are insensitive to frequency is difficult. Furthermore, in practical applications of bandpass signal cancelers, the frequency of the signal to be removed is often unknown. Other signal cancellation techniques using phase shift circuits encounter similar difficulties.
In U.S. Pat. No. 4,859,958, issued to the inventor hereof, capture effect associated with frequency demodulators is used in cooperation with PLL's to provide improved demodulation of all of several Frequency Modulation (FM) carriers including weaker signals in the presence of dominant carriers. In an application related to U.S. Pat. No. 4,859,958, co-pending with the present application and also by the inventor hereof, entitled "Multiple Reuse of an FM Band", Ser. No. 07/352,400, filed May 15, 1989, (now U.S. Pat. No. 4,992,747) a number of messages, which share transmitter power and each using the same frequency band simultaneously, can be received utilizing a plurality of cascaded PLL's.
In most applications, the function of a PLL is to track the frequency of the input signal. Referring to FIG. 1, when the loop is functioning, the frequency of the PLL oscillator output is slaved to the frequency of the input signal. The PLL is usable only when the frequency of the oscillator equals that of the input frequency. When the frequency of the oscillator equals the frequency of the input signal, the PLL is said to be in "lock" condition. However, the loop is locked only in frequency, not in phase, with the input signal.
The absence of phase lock in a typical prior art PLL can be shown with continuing reference to FIG. 1. PLL 10 requires that input signal v.sub.1 (t) have a periodic form, either sinusoid or square wave typically. Thus, v.sub.1 (t) is usually considered a bandpass signal which can be varied or modulated in amplitude or in frequency. In most instances, any amplitude variations are first removed by hard limiter 15 which causes the form of v.sub.1 (t), the input signal to PLL 10, to be a square wave having only FM.
With continuing reference to FIG. 1, phase detector 101 and lowpass filter 102 combine to convert the position in time of v.sub.4 (t) with respect to v.sub.1 (t) to a voltage, namely v.sub.3 (t). The position is established relative to a transition through zero volts. When v.sub.4 (t) and v.sub.1 (t) are sinusoids, this relative position is referred to as relative phase. The voltage v.sub.3 (t) can have positive or negative values depending on whether the zero volts position of v.sub.4 (t) occurs before or after that of v.sub.1 (t).
A non-zero value of v.sub.3 (t) causes the frequency of Voltage Controlled Oscillator (VCO) 103 to change from its reference value of f.sub.r Hz. Since v.sub.3 (t) is fed back to VCO 103, the adjustment of f.sub.r is just sufficient to achieve frequency lock condition. Therefore, the frequency of v.sub.4 (t) equals that of v.sub.1 (t).
Similarly, the operation of a PLL as a frequency demodulator may be explained by reference also to U.S. Pat. No. 4,859,958. In the transmitter, the change in message voltage m(t) with time causes a like change in the frequency of the transmitted carrier. The carrier is received as v.sub.1 (t) at the demodulator. If the frequency of v.sub.4 (t) is to equal that of v.sub.1 (t), then the output of lowpass filter 102, namely v.sub.3 (t), must follow m(t) or its inverse. Thus, the message variation is recovered as v.sub.3 (t).
As noted elsewhere in this specification, a typical prior art PLL is not locked in phase, but it rather is locked in frequency. Referring again to FIG. 1, let the frequency of v.sub.1 (t) be f.sub.1 Hz, not equal to f.sub.r Hz. When the PLL is locked, then f.sub.r .fwdarw.f.sub.r +.epsilon..sub.r =f.sub.1 Hz. This condition requires v.sub.3 .fwdarw.v.sub.3 +.epsilon..sub.3 volts. The generation of .epsilon..sub.3 volts requires a change in the time position of v.sub.4 (t) relative to that of v.sub.1 (t). The changed, or new, position is now referred to as the relative phase, .phi., of v.sub.4 (t) with respect to v.sub.1 (t) for the locked condition. Now, let f.sub.1 change so that f.sub.1 .fwdarw.f.sub.1 +.epsilon..sub.1. Applying the same reasoning which established lock condition of the PLL, then .phi..fwdarw..phi.+.DELTA..phi. when f.sub.1 .fwdarw.f.sub.1 +.epsilon..sub.1. Thus, a change in the frequency of input voltage v.sub.1 (t) is accompanied by an associated change in the phase of VCO 103 output voltage v.sub.4 (t) relative to v.sub.1 (t). Thus, a change in phase is necessary for a PLL to remain locked in frequency.